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FREE PROGRAMS FOR 8085 MICROPROCESSOR

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8085 MICROPROCESSOR TUTORIALS

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8085- INTERFACING TECHNIQUES

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8085 - THE COMPLETE DETAILS

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 THEORY :

Op-code fetch machine cycle of 8085 :

  • Each instruction of the processor has one byte opcode.
  • The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to fetch the opcode from memory.
  • Hence, every instruction starts with opcode fetch machine cycle.
  • The time taken by the processor to execute the opcode fetch cycle is 4T.
  • In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.
                Fig - Timing Diagram for Op-code Fetch Machine Cycle

Memory Read Machine Cycle of 8085:

  • The memory read machine cycle is executed by the processor to read a data byte from memory.
  • The processor takes 3T states to execute this cycle.
  • The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle.

                      Fig - Timing Diagram for Memory Read Machine Cycle

TIMING DIAGRAM:
I/O Read Cycle of 8085:
  • The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral, which is I/O, mapped in the system.
  • The processor takes 3T states to execute this machine cycle.
  • The IN instruction uses this machine cycle during the execution.

            Fig - Timing Diagram for Memory Write Machine Cycle
 
                            Fig - Timing Diagram for I/O Read Machine Cycle

TIMING DIAGRAM
  • The 8085 instructions consist of one to five machine cycles.
  • Actually the execution of an instruction is the execution of the machine cycles of that instruction in the predefined order.
  • The timing diagram of an instruction ate obtained by drawing the timing diagrams of the machine cycles of that instruction, one by one in the order of execution.
TIMING DIAGRAM OF 8085 INSTRUCTIONS :

Timing diagram for IN C0H.
  • Fetching the Opcode DBH from the memory 4125H.
  • Read the port address C0H from 4126H.
  • Read the content of port C0H and send it to the accumulator.
  • Let the content of port is 5EH. 

 



 Fig - Timing Diagram for Opcode Fetch Machine Cycle


Timing diagram for STA 526AH.
  • STA means Store Accumulator -The contents of the accumulator is stored in the specified address(526A).
  • The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH(see fig). - OF machine cycle
  • Then the lower order memory address is read(6A). - Memory Read Machine Cycle
  • Read the higher order memory address (52).- Memory Read Machine Cycle
  • The combination of both the addresses are considered and the content from accumulator is written in 526A. - Memory Write Machine Cycle
  • Assume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A.





Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states.

Instruction Cycle:

       The time required to execute an instruction is called instruction cycle.

Machine Cycle:

       The time required to access the memory or input/output devices is called machine cycle.

T-State:
  • The machine cycle and instruction cycle takes multiple clock periods.
  • A portion of an operation carried out in one system clock period is called as T-state.

MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 (seven) basic machine cycles. They are



  1. Opcode fetch cycle (4T)

  1. Memory read cycle (3 T)

  1. Memory write cycle (3 T)

  1. I/O read cycle (3 T)

  1. I/O write cycle (3 T)
  • Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085 processor executes an instruction, it will execute some of the machine cycles in a specific order.

  • The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T-states.

  • One T-state is equal to the time period of the internal clock signal of the processor.

  • The T-state starts at the falling edge of a clock.
TIMING DIAGRAM OF 8085 INSTRUCTIONS

Timing diagram for MVI B, 43H.
  • Fetching the Opcode 06H from the memory 2000H. (OF machine cycle)
  • Read (move) the data 43H from memory 2001H. (memory read)



Timing diagram for INR M

  • Fetching the Opcode 34H from the memory 4105H. (OF cycle)
  • Let the memory address (M) be 4250H. (MR cycle -To read Memory address and data)
  • Let the content of that memory is 12H.
  • Increment the memory content from 12H to 13H. (MW machine cycle)




 

I/O Write Cycle of 8085:

  • The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a peripheral, which is I/O, mapped in the system.
  • The processor takes, 3T states to execute this machine cycle.

                      Fig - Timing Diagram for I/O Write Machine Cycle

TIMING DIAGRAM

ADDRESSING MODES OF 8085
  • Every instruction of a program has to operate on a data.
  • The method of specifying the data to be operated by the instruction is called Addressing.
  • The 8085 has the following 5 different types of addressing.


               1. Immediate Addressing

               2. Direct Addressing

               3. Register Addressing

               4. Register Indirect Addressing

               5. Implied Addressing 

1. Immediate Addressing:
  • In immediate addressing mode, the data is specified in the instruction itself. The data will be a part of the program instruction.
  • EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP, 2700H.

2. Direct Addressing:
  • In direct addressing mode, the address of the data is specified in the instruction. The data will be in memory. In this addressing mode, the program instructions and data can be stored in different memory.
  • EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator; SHLD 3000H

3. Register Addressing:
  • In register addressing mode, the instruction specifies the name of the register in which the data is available.
  • EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.

4. Register Indirect Addressing:

  • In register indirect addressing mode, the instruction specifies the name of the register in which the address of the data is available. Here the data will be in memory and the address will be in the register pair.
  • EX. MOV A, M - The memory data addressed by H L pair is moved to A register. LDAX B.

5. Implied Addressing:
  • In implied addressing mode, the instruction itself specifies the data to be operated.
  • EX. CMA - Complement the content of accumulator; RAL



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